As structures to realize ultrafine MOSFETs having gate lengths of 30 nm or less, nanowire channel transistors (nanowire transistors) that can restrain short channel effects are expected to replace conventional plane-type transistors. Such a nanowire transistor includes: a silicon substrate; a buried oxide film formed on the silicon substrate; a semiconductor layer that is formed on the buried oxide film and includes one or more plate-like silicon nanowires to be channel regions; a gate insulating film formed on the side faces and upper faces of the nanowires; a gate electrode formed on the gate insulating film; gate sidewalls formed on both sides of the gate electrode (in the gate length direction); and a source region and a drain region that are formed in the nanowires and in the wide areas of the semiconductor layer, with the channel regions being interposed between the source region and the drain region. In the nanowires, the regions on which the gate electrode is formed operate as the channel regions. The channel regions each have a plate-like structure having a width (a length in the gate width direction) of approximately 3 nm to 25 nm and a height of approximately 3 nm to 40 nm. As the channel regions are covered with the gate electrode, the gate electrode has a large influence, and can restrain short channel effects. In a nanowire transistor, the three faces of the upper face and both side faces of each nanowire serve as a channel region. Therefore, nanowire transistors are also called tri-gate transistors.
In nanowire transistor manufacture, a SOI substrate is often used, instead of a bulk silicon substrate, mainly for the following two reasons. One of the reasons is that the buried oxide film can be used as the etching stopper in the nanowire processing. The other reason is that leak current between the source and drain in an OFF state can be certainly restrained by virtue of the existence of the buried oxide film as an insulator beneath the channel regions. However, a SOI substrate is more expensive than a bulk substrate, and leads to a cost increase in the entire manufacturing process.
To solve the above problem, a nanowire transistor including nanowires made of polycrystalline silicon on a bulk silicon substrate has been considered. This nanowire transistor differs from a nanowire transistor formed on a SOI substrate in that a SOI layer that is made of monocrystalline silicon and includes one or more nanowires is replaced with a polycrystalline silicon layer including one or more nanowires. In the polycrystalline silicon nanowires, the regions on which the gate electrode is formed operate as channel regions. However, due to the influence of crystal grain boundaries, polycrystalline silicon has much poorer mobility than monocrystalline silicon. Therefore, performance of a polycrystalline silicon nanowire transistor is much lower than performance of a nanowire transistor formed on a SOI substrate. Also, due to the influence of random crystal grain boundaries, variations in characteristics among devices are very large in polycrystalline silicon nanowire transistors.